1. Field of the Invention
The present invention relates generally to optical metrology and more particularly to characterizing and monitoring intra-field distortions of projection imaging systems used in semiconductor manufacturing.
2. Description of the Related Art
Today's lithographic processing requires ever tighter layer-to-layer overlay tolerances to meet device performance requirements. Overlay registration is defined as the translational error that exists between features exposed layer to layer in the vertical fabrication process of semiconductor devices on silicon wafers. Other names for overlay registration include, registration error and pattern placement error, and overlay error. Overlay registration on critical layers can directly impact device performance, yield and repeatability. Increasing device densities, decreasing device feature sizes and greater overall device size conspire to make pattern overlay one of the most important performance issues during the semiconductor manufacturing process. The ability to accurately determine correctable and uncorrectable pattern placement error depends on the fundamental techniques and algorithms used to calculate lens distortion, stage error, and reticle error.
A typical microelectronic device or circuit may consist of 20–30 levels or pattern layers. The placement of pattern features on a given level must match the placement of corresponding features on other levels, i.e., overlap, within an accuracy which is some fraction of the minimum feature size or critical dimension (CD). Overlay error is typically, although not exclusively, measured with a metrology tool appropriately called an overlay tool using several techniques. See for example, Semiconductor Pattern Overlay, N. Sullivan, SPIE Critical Reviews Vol. CR52, 160:188. The term overlay metrology tool or overlay tool means any tool capable of determining the relative position of two pattern features or alignment attributes, that are separated within 500 um (microns) of each other. The importance of overlay error and its impact to yield can be found elsewhere. See Measuring Fab Overlay Programs, R. Martin, X. Chen, I. Goldberger, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 64:71, March, 1999; New Approach to Correlating Overlay and Yield, M. Preil, J. McCormack, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 208:216, March 1999.
Lithographers have created statistical computer algorithms (for example, Klass II and Monolith) that attempt to quantify and divide overlay error into repeatable or systematic and non-repeatable or random effects. See Matching of Multiple Wafer Steppers for 0.35 Micron Lithography Using Advanced Optimization Schemes, M. van den Brink, et al., SPIE Vol. 1926, 188:207, 1993; A Computer Aided Engineering Workstation for Registration Control, E. McFadden, C. Ausschnitt, SPIE Vol. 1087, 255:266, 1989; Semiconductor Pattern Overlay, supra; Machine Models and Registration, T. Zavecz, SPIE Critical Reviews Vol. CR52, 134:159. An overall theoretical review of overlay modeling can be found in Semiconductor Pattern Overlay, supra.
Overlay error is typically divided into the following two major categories. The first category, inter-field or grid overlay error, is concerned with the actual position of the translation and rotation, or yaw, of the image field as recorded in the photoresist on a silicon wafer using an exposure tool, i.e., stepper or scanner. Translation is referenced from the nominal center of the water while yaw is referenced with respect to the nominal center at each field. See FIG. 19. The alignment of the device pattern on the silicon wafer depends on the accuracy of the stepper or scanner wafer stage, reticle stage and any interaction between them.
The second category, intra-field overlay error, is the positional offset of an individual point inside a field referenced to the nominal center of an individual exposure field, as illustrated in FIG. 20. The term “nominal center” means the machine programmed stepping position. Intra-field overlay errors are generally related to lens aberrations or distortions, scanning irregularities, and reticle alignment. It is common practice to make certain assumptions concerning the magnitude and interaction of stage error and lens distortion error in modern overlay algorithms that calculate lens distortion. The common rule is: “trust the accuracy of the stage during the creation of the overlay targets by making the simple assumption that only a small amount of stage error is introduced and can be accounted for statistically”. See A “Golden Standard” Wafer Design for Optical Stepper Characterization, K. Kenp et al., SPIE Vol. 1464, 260:266, 1991; Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, M. Van den Brink, et al., SPIE Vol. 921, 180:197, 1988. When applied to measurements of intra-field distortion this technique is called stage metered measurement of lens distortion.
It is important for this discussion to realize that most overlay measurements are made on silicon product wafers after each photolithographic process, prior to final etch. Product wafers cannot be etched until the resist target patterns are properly aligned to the underlying target patterns. See Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology Tool Throughput, J. Pellegrini, SPIE Vol. 3677, 72:82. Manufacturing facilities rely heavily on exposure tool alignment and calibration procedures to help insure that the stepper or scanner tools are aligning properly; See Stepper Matching for Optimum Line Performance, T. Dooly et al., SPIE Vol. 3051, 426:432, 1997; Mix-and-Match: A Necessary Choice, R. DeJule, Semiconductor International, 66:76, February 2000; Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, supra. Inaccurate overlay modeling algorithms can corrupt the exposure tool calibration procedures and degrade the alignment accuracy of the exposure tool system. See Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology Tool Throughput, supra.
Over the past 30 years the microelectronics industry has experienced dramatic rapid decreases in critical dimension by moving constantly improving photolithographic imaging systems. Today, these photolithographic systems are pushed to performance limits. As the critical dimensions of semiconductor devices approach 50 nm the overlay error requirements will soon approach atomic dimensions. See Life Beyond Mix-and-Match: Controlling Sub-0.18 micron Overlay Errors, T. Zavecz, Semiconductor International, July, 2000. To meet the needs of next generation device specifications new overlay methodologies will need to be developed. In particular, overlay methodologies that can accurately separate out systematic and random effects and break them into assignable causes will greatly improve device process yields. See A New Approach to Correlating Overlay and Yield, supra.
In particular, those new overlay methodologies that can be implemented into advanced process control or automated control loops will be most important. See Comparisons of Six Different Intra-field Control Paradigms in an Advanced Mix and Match Environment, J. Pellegrini, SPIE Vol. 3050, 398:406, 1997; Characterizing Overlay Registration of Concentric 5× and 1× Stepper Exposure Fields Using Inter-Field Data, F. Goodwin et al., SPIE Vol. 3050, 407:417, 1997. Finally, another area where quantifying lens distortion error is of vital concern is in the production of photomasks or reticles during the electron beam manufacturing process. See Handbook of Microlithography and Microfabrication, P. Rai-Choudhury, Vol. 1, pg. 417, 1997.
Semiconductor manufacturing facilities generally use some version of the following complex overlay procedure to help determine the magnitude of intra-field distortion independent of other sources of systematic overlay error for both photolithographic steppers and scanners. The technique has been simplified for illustration. See Analysis of Image Field Placement Deviations of a 5× Microlithographic Reduction Lens, D. MacMillen et al., SPIE Vol. 334, 78:89, 1982. FIGS. 3 and 4 show typical sets of overlay targets, including—one large or outer box and one small or inner target box. FIG. 1 shows a typical portion of a distortion test reticle used in the prior art. It should be noted that the chrome target patterns on most reticles are 4 or 5 times larger as compared with the patterns they produce at the image plane, this simply means modern stepper and scan systems (scanners) are reduction systems. Further, for purposes of discussion, it is assumed that the reticle pattern is geometrically perfect, (in practice, the absolute positions of features on the reticle can be measured and the resulting errors subtracted off). First, a wafer covered with photoresist is loaded onto the wafer stage and globally aligned. Next, the full-field image of the reticle, in FIG. 2a is exposed onto the resist-coated wafer in FIG. 25. For purposes of illustration, we assume that the distortion test reticle consists of a 5×5 array of outer boxes evenly spaced a distance M*P, across the reticle surface. See FIG. 2a. It is typically assumed that the center of the optical system is virtually aberration free. See Analysis of Image Field Placement Deviations of a 5× Microlithographic Reduction Lens, supra. With this assumption, the reticle, in FIG. 2a, is now partially covered using the reticle blades, See FIG. 18, in such a way that only a single target at the center of the reticle field, box A, in FIG. 2a, is available for exposure. Next, the wafer stage is moved in such a way as to align the center of the reticle pattern directly over the upper left hand corner of the printed 5×5 outer box array, wafer position 1, FIG. 25. The stepper then exposes the image of the small target box onto the resist-coated wafer. If the wafer stage, optical system, and scanning dynamics were truly perfect then the image of the small target box would fit perfectly inside the image of the larger target box from the previous exposure, as illustrated in FIGS. 5, 6, and 25.
At this point the stepper and wafer stage are programmed to step and expose the small target box in the 5×5 array where each exposure is separated from the previous one by the stepping distance P. With the assumption of a perfect stage, the final coordinates of the small target boxes are assumed to form a perfect grid, where the spacing of the grid is equal to the programmed stepping distance, P. Finally, if the first full-field exposure truly formed a perfect image, then the entire 5×5 array of smaller target boxes would fit perfectly inside the 5×5 array of larger target boxes as illustrated in FIG. 6. Since the first full-field exposure pattern is in fact distorted due to an imperfect imaging system, and scanner system, the actual position of the larger target box will be displaced relative to the smaller target boxes for example, as shown in FIG. 6. The wafer is then sent through the final few steps of the photographic process to create the final resist patterned overlay targets. The intra-field overlay error at each field position can be measured with a standard optical overlay tool. Using the models described below, in Equations 1 and 2, the overlay data is analyzed and the lens distortion error is calculated.
The following inter-field and intra-field modeling equations are commonly used to fit the overlay data using a least square regression technique. See Analysis of Image Field Placement Deviations of a 5× Microlithographic Reduction Lens, supra; Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology Tool Throughput, supra.dxf(xf,yf)=Tx+s*xf−q*yf+t1*xf2+t2*xf*yf−E*(xf3+xf*yf2)  (eq. 1)dyf(xf,yf)=Ty+s*yf+q*xf+t2*yf2+t1*xf*yf−E*(yf3+yf*xf2)  (eq. 2)where    (xf,yf)=intra-field coordinates    (dxf, dyf)(xf,yf)=intra-field distortion at position (xf, yf)    (Tx, Ty)=(x,y) intra-field translation    s=intra-field overall scale or magnification    q=intra-field rotation    (t1, t2)=intra-field trapezoid error    E=intra-field lens distortion.
A problem with the this technique is two-fold, first, it is standard practice to assume that the wafer stage error is very small, randomly distributed, and can be completely accounted for using a statistical model. See Analysis of Image Field Placement Deviations of a 5× Microlithographic Reduction Lens, supra; A “Golden Standard” Wafer Design for Optical Stepper Characterization, supra; Matching Management of Multiple Wafer Steppers Using a Stable Standard and a Matching Simulator, M. Van den Brink et al., SPIE Vol. 1087, 218:232, 1989; Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, supra. In general, positional uncertainties in the wafer stage introduce both systematic and random errors, and since the intra-field is measured only in reference to the lithography tool's wafer stage, machine to machine wafer stage differences show up as inaccurate lens distortion maps. Secondly, the assumption that lens distortion is zero at the center of the lens is incorrect. Furthermore, the model represented by Equations 1 and 2 is entirely unsuited to modeling scanner scale overlay errors—typically the intra-field distortion model accounts only for the scanner skew and scanner scale overlay errors—in general, the synchronization errors between the reticle stage and wafer stage introduce more complex errors described below.
A technique for stage and ‘artifact’ self-calibration is described in See Self-Calibration in Two-Dimensions: The Experiment, M. Takac, et al., SPIE Vol. 2725, 130:146, 1996; Error Estimation for Lattice Methods of Stage Self-Calibration, M. Raugh, SPIE Vol. 3050, 614:625, 1997. It consists of placing a plate (artifact) with a rectangular array of measurable targets on a stage and measuring the absolute positions of the targets using a tool stage and the tool's image acquisition or alignment system. This measurement process is repeated by reinserting the artifact on the stage but shifted by one target spacing in the X-direction, then repeated again with the artifact inserted on the stage shifted by one target spacing in the Y-direction. Finally, the artifact is inserted at 90-degrees relative to its' initial orientation and the target positions measured. The resulting tool measurements are a set of (x, y) absolute positions in the tool's nominal coordinate system. Then, the absolute positions of both targets on the artifact and a mixture of the repeatable and non-repeatable parts of the stage x, y grid error are then determined to within a global translation (Txg, Tyg), rotation (qg) and overall scale ((sxg+syg)/2) factor. A drawback to this technique is that it requires that the measurements be performed on the same machine that is being assessed by this technique. Furthermore, this technique requires measurements made on a tool in absolute coordinates; the metrology tool measures the absolute position of the printed targets relative to it's own nominal center; so absolute measurements are required over the entire imaging field (typical size greater than about 100 mm2).
Another technique for the determination of intra-field distortion is the method of A. H. Smith et al. (“Method And Apparatus For Self-Referenced Projection Lens Distortion Mapping”, U.S. patent application Ser. No. 09/835,201, filed Apr. 13, 2001). It is a self-referencing technique that can be utilized with overlay metrology tools in a production environment. For diagnosing the intra-field scanner distortion in the presence of significant scanner non-repeatability, this technique teaches the use of a special reticle that has reduced optical transmission that is multiply scanned producing sub-Eo exposures on the wafer. This technique can be used to accurately determine the repeatable part of the scanner intra-field distortion but not that part of the intra-field distortion that changes from scan to scan (a simple example of which is the scanner y-magnification).
Another drawback to these techniques to determine the intra-field error is that they use the scanner itself as the metrology tool. Due to the cost of scanners, which can exceed 10 million dollars, it is desirable to have a technique for intra-field error that does not use the scanner itself as the metrology tool for determining intra-field distortion but utilizes relatively inexpensive overlay metrology tools. Furthermore, it is desirable that the technique be easy to perform and thereby allowing it to be used in a production environment by the day-to-day operating personnel. It is further desirable to have a technique that can distinguish between the non-repeatable parts of the scanner intra-field distortion.
Other references that discuss aspects of intra-field distortion include: New 0.54 Aperture I-Line Wafer Stepper with Field by Field Leveling Combined with Global Alignment, M. Van den Brink et al., SPIE Vol. 1463, 709:724, 1991; Impact of Lens Aberrations on Optical Lithography, T. Brunner; Lens Matching and Distortion Testing in a Multi-Stepper, Sub-Micron Environment; A. Yost et al., SPIE Vol. 1087, 233:244, 1989; The Attenuated Phase Shift Mask, B. Lin; Projection Optical System for Use in Precise Copy, T. Sato et al., U.S. Pat. No. 4,861,148, Aug. 29, 1989; Method of Measuring Bias and Edge Overlay Error for Sub 0.5 Micron Ground Rules, C. Ausschnitt et al., U.S. Pat. No. 5,757,507, May 26, 1998.
Therefore there is a need for an effective, and efficient, way to determine the scanner intra-field distortion or translation errors of a projection system.